The invention relates to an information processing system in which architecture is employed which separates a bus controller and a memory controller from the central processing unit, thus improving system throughput.
There have been proposed many types of data transfer systems connecting, for data processing, various units in an information processing system such as a main memory, a central processing unit, and a plurality of input/output units.
One form of such data transfer system is shown in FIG. 1. The information processing system shown in FIG. 1 includes a memory bus 3 connecting an arithmetic control unit (ACU) 1 and a plurality of memory units Ml to Mn designated by reference numeral 2, a direct memory access (DMA) bus 5 connecting the ACU 1 and a plurality of input/output units I/Ol to I/On designated by reference numeral 4, and an input/output bus 6. The ACU 1 inputs address data and a control signal through the memory bus 3 to one of the memory units 2 to access the memory unit. The ACU 1 issues an input/output control signal (an address command interrupt signal) to one of the input/output units 4, through the input/output bus 6. The input/output unit 4 responds to the input/output control signal from the ACU 1 to transfer an address data control signal to one of the memory units 2 by way of the DMA bus 5. The information processing system in FIG. 1 is so constructed that the memory bus 3, the DMA bus 5 and the input/output bus 6 are all controlled by the ACU 1. For this, the logic circuitry of the ACU 1 is complex. Additionally, the operations of the respective bus controls and the ACU 1 are conducted in series mode so that the throughput of the system is restricted.
Another example of the type of data transfer system in question is illustrated in FIG. 2. The data transfer system in FIG. 2 is the so-called common bus system in which a plurality of memory units Ml to Mn designated by reference numeral 11 and a plurality of input/output systems I/Ol to I/On designated by reference numeral 12 are connected by a common bus 13. In this system, the ACU 14 controls the common bus 13, and the necessary control signals are all transferred through the common bus 13. This type of data transfer system is disclosed for example in U.S. Pat. No. 3,710,324. This system, however, has the disadvantage that, because of the restriction of bus occupation, which limits the transfer rate, system throughput is restricted particularly in a relatively large scale system.